The present invention relates generally to two-level caches, and more particularly to synchronization of a two-level cache in a graphics processing system.
Graphics processing systems process large amounts of data. This data is often texture data. Textures represent surface qualities of geometric objects, and are used to provide increased realism in 3D graphics. Texture information is often stored in the form of texture maps with the texture map being comprised of texture elements (texels). Texels are used in conjunction with geometric information of an object to determine color and intensity of a pixel displayed on a display device. Often multiple texels from a single texture map are used, or blended, to determine the display characteristics of a pixel. In addition, at times texels from more than one texture map are used to determine the display characteristics of any one pixel. Therefore, color and intensity of a single pixel may be formed through blending multiple texels and these texels may come from more than one texture map.
Texture data is often resident in system memory. System memory, however, is a shared resource. In computer systems having a dedicated bus for graphics processing systems, other devices may attempt to access data used by the graphics processing system. This may increase data access time for the graphics processing system. In computer systems in which graphics processing system shares a common system bus with other devices, the common bus may be in use by other devices when the graphics processing system attempts to make use of system memory. In addition, requests for data from system memory may take excessive amounts of time. Accordingly, accessing system memory is a potential performance bottleneck for graphics processing systems.
A graphics cache dedicated to storing graphics data is sometimes used to enhance accessibility of graphics data by a graphics processing system. The graphics cache is provided graphics data from the system memory prior to a demand by the graphics processing system. The graphics system, therefore, has the graphics data available for use when desired, thereby reducing the need to promptly access system memory and reducing problems associated with memory latency.
A graphics cache, however, is often too small to store an entire texture map. Increasing the size of the graphics cache to allow for storage of an entire texture map is not always a viable solution. Increasing the size of the graphics cache may result in decreased performance as cache access time generally increases with cache size. In addition, increased cache size requires increased space within a chip, and chip space is often at a premium.
In order to provide increased cache size without significantly affecting cache performance, caches for central processing units (CPUs) are sometimes in the form of two-level caches. In a two-level cache a first level cache of the data, such as a graphics engine. A second level cache, generally containing significantly more data, supplies data to the first level cache. The use of a two-level cache provides benefits in terms of increased data availability and decreased memory access time. The use of a two-level cache, however, also creates issues with respect to the transfer of the data to, and the deletion of data from, the cache system.
Beneficially, data most likely to be immediately required for use by the user is present in the level one cache, with data likely to be required for use in the near future in the level two cache. By transferring appropriate portions of the texture map between the two caches, the graphics processing system can have the data available in the graphics cache, resulting in reduced memory access time. Without appropriate determination of which data to transfer, and which data to overwrite, however, the benefits of a two-level cache may be reduced.
The present invention is a graphics processing system having a synchronized two-level cache.
One embodiment of the present invention is a method of performing graphics processing using a first cache comprised of first cache lines and a second cache comprised of second cache lines. Each of the first cache lines is associated with first cache flags. Each of the second cache lines is associated with second cache flags. An availability of graphics data in the first cache and second caches are checked. Then, first and second cache flags are updated based on availability of the graphics data in the first and second caches.
Another embodiment of the present invention is a method of performing graphics processing where the first cache lines are divided into a plurality of slots and a plurality of first sets. The second cache lines are also divided into a plurality of second sets.
Yet another embodiment of the present invention is a method of performing graphics processing where the first cache flags comprise a plurality of first reference counters and a plurality of first age status stacks. The second cache flags comprise a plurality of second reference counters and a plurality of second age status stacks.
Yet another embodiment of the present invention is a method of performing graphics processing where availability of the graphics data in the first and second caches are ascertained. Texel coordinates are received. First and second tag addresses are ascertained from the texel coordinates. The first tag addresses are compared with first content identities of the first cache lines belonging to the associated one of the plurality of first sets of the associated one of the plurality of slots. Based on the results of the comparisons, a first graphics data available status or a first graphics data not available status is returned. The second tag addresses are compared with second content identities of the second cache lines belonging to the associated one of the plurality of second sets. Based on the results of the comparisons, a second graphics data available status or a second graphics data not available status is returned.
Yet another embodiment of the present invention is a method of performing graphics processing where first cache flags are updated based on availability of the graphics data in the first and second caches. First and second age statuses become youngest when updated based on the availability of the graphics data in the first and second caches. The first and second reference counters are reset or incremented based on the availability of the graphics data in the first and second caches. Oldest first and second cache lines are selected and updated to be youngest depending on the availability of the graphics data in the first and second caches.
Yet another embodiment of the present invention is a graphics processing system comprising a first cache, a second cache, an engine and a frame buffer. The first and second caches contain a plurality of first and second cache lines. The first cache is partitioned into a plurality of slots. The first cache receives data from a system memory. The second cache receives the data from the first cache. The first cache and the second caches are synchronized with each other.
Yet another embodiment of the present invention is a graphics processing system comprising an age status tracking means, first and second reference counters and first and second internal counters. The age status tracking means keep track of a least recently used second cache line and a least recently used first cache line. First and second reference counters keep track of how many times data in the respective first and second cache lines have been requested. The first and second internal counters keep track of how many times requested data in the respective first and second cache lines have been transferred. The least recently used first and second cache lines are selected to be overwritten with data to be received.
Yet another embodiment of the present invention is a graphics processing system comprising a first cache, a second cache, an engine and a frame buffer. The first and second caches contain a plurality of first and second cache lines. The first cache is partitioned into a plurality of slots. The first cache receives texture data from a system memory. The second cache receives the texture data from the first cache. The first cache and the second caches are synchronized with each other.
Yet another embodiment of the present invention is a synchronized two level cache system in a graphics processor generating display information based on graphics data for an area comprising a first cache comprised of first cache lines containing graphics data and a second cache comprised of second cache lines containing graphics data. The first and second cache lines each contain data for contiguous regions of the area.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.